1/4 rev. b structure product name model name function silicon monolithic integrated circuits boost dc/dc converter lsi for blu-ray BD9997FVT (1) the output voltage can be set by external resistance. (2) internal power mos transistor with backgate control functio n (3) inrush current reduction (4) integrated soft start (5) built-in protection function nmos overcurrent limit, overvoltage mute, thermal shutdown, output ground short protection (6) uvlo operation at low power-supply voltage (7) easy assembly small sized package tssop-b8 (8) built-in discharge function (9) function of output intercepti on(at shutdown, at overvoltage ) absolute maximum ratings (ta=25) item symbol limit unit supply voltage vcc -0.37 v power dissipation 1 pd 0.625 w operating temperature range topt -25+85 storage temperature range tstg -55+150 input voltage range on sw vinsw -0.315 v input voltage range on vout vinout -0.315 v input voltage range on fb vinfb -0.3vcc+ 0.3 v ampout terminal maximum input voltage vinampout -0.3vcc+ 0.3 v xshdn terminal maximum input voltage vinshdn -0.3vcc+ 0.3 v junction temperature tjmax +150 1 while mounted on glass-expoxy boardrohm standard board70 701.6[mm 3 ] operating conditions (ta25) item symbol min. typ. max. unit supply voltage vcc 4.5 5.0 5.5 v output current1 25 iout1 - - 0.15 a output current2 35 iout2 - - 0.10 a output current3 45 iout3 - - 0.20 a 2 vin=4.5[v] vout=7.5[v] (l=22[uh]) 3 vin=4.5[v] vo ut=11.0[v] (l=22uh) 4 vin=4.5[v] vout=8.1[v] (l=10uh) 5 do not, however e xceed pd.
2/4 rev. b electric characteristics unless otherwise specified, v cc=5.0[v], vout=5.0[v], ta=25[ ] parameter symbol limit unit condition min. typ. max. current consumption icc1 4.0 6.3 9.5 ma vcc=5.0[v], fb=2.5[v], no load current consumption icc2 2.3 3.7 5.2 ma vcc=5.0[v], fb=0[v], no load current consumption (shutdown mode) icc3 1 10 a vcc=5.0[v], xshdn=gnd or open output voltage range voutr vcc 12.0 v soft start beginning time tsoft 3.5 6.0 8.5 ms vcc=5.0[v], fb=0 [v] errvref voltage errvref 0.582 0.600 0.618 v oscillator frequency sawo 400 650 900 khz maximum duty cycle dmax 65 80 90 % ampout maximum output voltage vampouth 2.00 2.30 2.60 v ampout minimum output voltage vampoutl 0.03 0.20 v pmos on resistance ronp 0.36 0.60 0.84 vout=9.0[v] nmos on resistance ronn 0.30 0.50 0.70 vout=9.0[v] uvlo detection voltage vuvlo1 3.35 3.55 3.75 v vcc falling uvlo return voltage vuvlo2 3.45 3.65 3.85 v vcc rising xshdn input threshold voltage vthxshdn 0.92 1.53 2.14 v xshdn pull down resister rxshdn 7.0 10.0 13.0 k
3/4 rev. b package outline block diagram terminal no./terminal name terminal no terminal name 1 vout 2 fb 3 ampout 4 gnd 5 xshdn 6 vcc 7 pgnd 8 sw output control 1 vout xshdn current limit backgate control 8 7 6 5 2 3 4 fb ampout gnd vcc pgnd sw soft start saw errvref dtc lot no. 9 9 9 7 3.00.1 max 3.35 (include. burr) 6.40.2 4.40.1 0.525 1pin mark 0.65 0.245 +0.05 -0.04 0.145 +0.05 -0.03 1.2max 1.00.05 0.10.05 1 2 3 4 5 6 7 8 44 1.0 1.2 0.08 0.08 (unit: mm) 0.5 0.15
4/4 rev. b operation notes 1 about grand potential set pgnd and gnd to equal potent ial.the ground line is where th e lowest potential and transient voltages are connected to the ic. 2about starting keep light load at vout output while start-up. 3about board pattern use separates ground lines for small control signals and high c urrent outputs. because these high current outputs that flows to the wire impedance changes the gnd voltage for control signal. therefore each ground of ic must be connected at one point on the set circuit board. as for gnd of external part s, its similar to the above-m entioned. the characteristics of dc/dc converter might influenced by surrounding components and board pattern. consider the effects from surroundings while design. make vcc,pgnd and gnd impedance sufficiently low solder reserve to gnd on set circuit board. 4about peripheral circuit bypass capacitor between power supply and ground should be use low esr ceramic capacitor and placed close to the ic pin as possible. external components such as l and c is necessary to be placed as near to the ic as possible with shortest distance. monitor the output voltage at both end of capacitor connected to vout.pmos over current limit must not be built into, and the over current must not flow to pmos. please have safe countermeasure such as adding poly switch and fuse to avoid fro m over stressing. 5 about absolute maximum rating exceeding supply voltage and oper ating temp. over absolute maximum ratings may cause degradation of ic and even may destroy the ic. if spe cial mode such that exceeding absolute maximum ratings is expected, please have safe countermeasure such as adding poly switch and fuse to avoi d from over stressing. 6about heat design do not exceed the power dissipati on (pd) of the package specifi cation rating under actual operation. 7 about short between terminals and the mis-installation while mounting ic on the board, check direction and position of the ic. if inadequately mo unted, the ic may destroy. moreover this ic might be dest royed when dust short the termina ls between pins or pin and ground. 8 about operation in stron g electromagnetic field strong electromagnetic radiation can cause operation failures. 9 about heat interception circuit (tsd) the tsd is activated when the j unction temperature (tj) reaches 175 and the output terminal is switched to hi-z. the tsd circuit aims to intercept ic from high temperature. the gua rantee and protection of ic are not purpose. therefore, please do not use this ic after tsd circuit operates, nor use i t for assumption that op erates the tsd circuit. 10 about inspection by set substrate the stress might hang to ic by connecting the capacitor to the terminal w ith low impedance. then, please discharge electricity in each and all process. moreover, in the inspectio n process, please turn off the power before mounting the ic, an d turn on after mounting the ic. in addition, please take into co nsideration the countermeasures for electrostatic damage, such as giving the earth in assembly p rocess, transportation or preservation. 11about each input terminal this ic is a monolithic ic, and has p + isolation and p substrate for the element separation. therefor e, a parasitic pn junction is firmed in this p-layer and n- layer of each element. when the gnd voltage potential is greater than the voltage potential at terminals a or b, the pn junction operates as a parasitic diode . in addition, the parasitic np n transistor is formed in said parasitic diode and the n layer of surrounding elements close t o said parasitic diode. these parasitic elements are formed in the ic because of the voltage relation. the parasitic element o perating causes the wrong operation and destruction. therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than gnd (p substrate). please do not apply the voltage to the input terminal when the power Csupply voltage is not impressed. moreover, please impress each input terminal lower than the pow er-supply voltage or equal t o the specified range in the guaranteed voltage when the power- supply voltage is impressing. .
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